COA Question Paper-GATE & PSU Exam

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Here, We will see (Computer Organization and Architecture) COA Question Paper from the previous year’s exam and the syllabus of Computer Organization and Architecture for GATE and PSU Exam.

1. Computer Organization and Architecture

Computer Organization and Architecture (COA) testing candidates’ understanding of hardware functionality, system design, and operational efficiency. This subject bridges theoretical concepts with real-world applications, making it essential for both academic and industry roles.

2. Computer Organization and Architecture Syllabus

The COA Questions asked in the GATE and PSU Exam focused on topics:

  1. Machine Instructions & Addressing Modes: Basics of instruction sets, operand addressing, and register structures.
  2. ALU, Data Path, & Control Unit: Design of arithmetic logic units and control mechanisms.
  3. Instruction Pipelining: Stages of pipelining, hazards (structural, data, control), and optimization techniques.
  4. Memory Hierarchy: Cache memory (associativity, hit/miss ratios), main memory, secondary storage, and virtual memory.
  5. I/O Interfaces: Interrupts, DMA modes, and I/O processor communication

COA Question Paper-GATE & PSU Exam

Q. The example of implied addressing is

  1. Stack addressing
  2. Indirect addressing
  3. Immediate addressing
  4. None of the above
Answer

Stack addressing
NIELIT 2016 DEC Scientist B (IT)

Q. A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor?

  1. Pointers.
  2. Arrays.
  3. Records.
  4. All of these.
Answer

All of these.
NIELIT 2016 MAR Scientist B

Q. INC A(Increase register A by 1) is an example of which of the following addressing modes?

  1. Immediate addressing
  2. Indirect addressing
  3. Implied addressing
  4. Relative addressing
Answer

Implied addressing
NIELIT 2017 DEC Scientist B

Q. A two-word instruction is stored in a location 1. The operand part of instruction holds 1. If the addressing mode is relative, the operand is available in the location

  1. A+B+2
  2. A+B+1
  3. B+1
  4. A+B
Answer

A+B+2
NIELIT 2017 DEC Scientist B

Q. Consider the expression (a-1)*(((b+c)/3))+d)). Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture, in which
i. only load and store instructions can have memory operands and
ii. arithmetic instructions can have only register or immediate operands.
The value of X is _____________ .

  1. 2
  2. 1
  3. 4
  4. 3
Answer

2
NIELIT 2022 April Scientist B

Q. In _______ machine is executing operating system instructions:

  1. System mode
  2. User mode
  3. Normal mode
  4. Safe mode
Answer

System mode
NIELIT 2021 Dec Scientist B

Q. Identify the true statement from the given statements. Program relocation at run time
1. requires transfer of complete block to some memory locations
2. requires both base address and relative address
3. requires only absolute address

  1. 1
  2. 1 and 2
  3. 1, 2 and 3
  4. 1 and 3
Answer

1 and 2
NIELIT 2018

Q. When a cache is 10 times faster than main memory, and the cache can be used 70% of the time, how much speed can be gained using cache?

  1. ≃10
  2. ≃0.3
  3. ≃0.7
  4. ≃2.7
Answer

≃2.7
NIELIT 2021 Dec Scientist B

Q. Consider a system with page size p and average process size m and the size of each page table entry is e. What is the amount of space required by a page table?

  1. me/p
  2. mp/e
  3. mpe
  4. pe/m
Answer

me/p
NIELIT 2021 Dec Scientist A

Q. In the following addressing mode, which of them performs better for accessing an array?

  1. Register addressing mode
  2. Direct addressing mode
  3. Displacement addressing mode
  4. Index addressing mode
Answer

Index addressing mode
NIELIT Scientific Assistant A 2020 November

Q. In a cache memory if a total number of sets is ‘s’, then the set offset is:

  1. 28
  2. log2s
  3. s2
  4. s
Answer

log2s
NIELIT 2017 DEC Scientist B

Q. In time division switches if each memory access takes 100ns and one frame period is 125µs, then the maximum number of lines that can be supported is

  1. 625 lines
  2. 1250 lines
  3. 2300 lines
  4. 318 lines
Answer

625 lines
NIELIT 2017 OCT Scientific Assistant A (IT)

Q. When a subroutine is called, the address of the instruction following the CAL instruction is stored in/on the

  1. Stack pointer
  2. Accumulator
  3. Program counter
  4. Stack
Answer

Program counter
NIELIT 2016 MAR Scientist C

Q. How many wires are threaded through the cores in a coincident-current core memory?

  1. 2
  2. 3
  3. 4
  4. 6
Answer

4
NIELIT 2017 July Scientist B (CS)

Q. The process of entering data into a storage location

  1. causes variation in its address number
  2. adds to the contents of the location
  3. is called a readout operation
  4. is destructive of previous contents
Answer

is destructive of previous contents
NIELIT 2016 MAR Scientist C

Q. Serial access memories are useful in applications where

  1. data consists of numbers
  2. short access time is required
  3. each stored word is processed differently
  4. data naturally needs to flow in and out in serial form
Answer

data naturally needs to flow in and out in serial form
NIELIT 2016 MAR Scientist C

Q. If a processor does not have any stack pointer register, then

  1. it cannot have subroutine call instruction
  2. it can have subroutine call instructions, but no nested subroutine calls
  3. nested subroutine calls are possible, but interrupts are not
  4. all sequences of subroutine calls and also interrupts are possible
Answer

it cannot have subroutine call instruction
NIELIT 2016 MAR Scientist C

Q. In the case of the zero-address instruction method the operands are stored in _________ .

  1. Registers
  2. Accumulators
  3. Push down stack
  4. Cache
Answer

Push down stack
NIELIT 2021 Dec Scientist A

Q. The part of machine-level instruction, that tells the central processor what has to be done, is

  1. Operation code
  2. Address
  3. Locator
  4. Flip-Flop
Answer

Operation code
NIELIT 2017 July Scientist B (CS)

Q. If the period of a signal is 100ms. Then its frequency in Hertz is __

  1. 10
  2. 100
  3. 1000
  4. 10000
Answer

10
NIELIT 2018

Q. The ALU uses _________ to store the intermediate result

  1. Cache
  2. Registers
  3. Accumulators
  4. Stack
Answer

Accumulators
NIELIT 2018

Q. In what module multiple instances of execution will yield the same result even if one instance has not terminated before the next one has begun?

  1. Non reusable module
  2. Serially usable
  3. Re-enterable module
  4. Recursive module
Answer

Re-enterable module
NIELIT 2016 MAR Scientist B

Q. Identify the true statements from the given statements, Program relocation at run time
(i) requires to transfer of the complete block to some memory locations
(ii) requires both base address and relative addresses
(iii) requires only absolute addresses

  1. i
  2. i and ii
  3. i, ii and iii
  4. i and iii
Answer

i and ii
NIELIT SB_2018

Q. Process that periodically checks the status of an I/O device, is known as

  1. Cold swapping
  2. I/O instructions
  3. Polling
  4. Dealing
Answer

Polling
NIELIT 2016 DEC Scientist B (CS)

Q. A microprogrammed control unit

  1. is faster than a hardwired unit
  2. Facilitates easy implementation of new instruction
  3. is useful when small programs are to be run
  4. All of the above
Answer

Facilitates easy implementation of a new instruction
NIELIT 2017 OCT Scientific Assistant A (CS)

Q. Which of the following is a desirable property of the module?

  1. Independency
  2. Low cohesiveness
  3. High Coupling
  4. Multifunctional
Answer

Independency
NIELIT 2017 OCT Scientific Assistant A (CS)

Q. Consider the following sequence of micro-operations:
MBR←PC
MAR←X
PC←Y
MEMORY←MBR
Which one of the following is a possible operation performed by this sequence?

  1. Instruction Fetch
  2. Operand Fetch
  3. Conditional Branch
  4. Initiation of interrupted service
Answer

Operand Fetch
NIELIT 2021 Dec Scientist A

Q. If the size of the logical address space is 2m and the page size is 2n addressing units, then the high order of a logical address designate the ________ .

  1. offset
  2. page no
  3. frame no
  4. physical address
Answer

page no
NIELIT 2021 Dec Scientist B

Q. A pipeline has having speed up factor as 10 and operating with efficiency of 80%.What will be the number of stages in the pipeline?

  1. 10
  2. 8
  3. 13
  4. None
Answer

13
NIELIT 2017 OCT Scientific Assistant A (IT)

Q. Where does the swap reside?

  1. RAM
  2. ROM
  3. DISK
  4. On-chip cache
Answer

DISK
NIELIT 2016 DEC Scientist B (CS)

Q. The addressing mode used in an instruction of the form ADD X Y, is

  1. Direct
  2. Absolute
  3. Indirect
  4. Indexed
Answer

Indexed
NIELIT 2016 DEC Scientist B (CS)

Q. A 3.5-inch micro floppy high-density disk contains the data _____

  1. 720 MB
  2. 1.44 MB
  3. 720 KB
  4. 1.44 KB
Answer

1.44 MB
NIELIT 2017 DEC Scientific Assistant A

Q. What is the average Access Time for a drum rotating at 400 revolutions per minute?

  1. 2.5 milliseconds
  2. 5.0 milliseconds
  3. 7.5 milliseconds
  4. 4.0 milliseconds
Answer

7.5 milliseconds
NIELIT 2017 July Scientist B (CS)

Q. Consider a system with three frames in memory and following memory references in the working set
2 1 2 3 5 4 1 3 4 2 1
How many page faults will be there if we used second chance page replacement algorithm?

  1. 7
  2. 8
  3. 9
  4. 10
Answer

9
NIELIT 2021 Dec Scientist A

Q. Which level of RAID refers to disk mirroring with block striping?

  1. RAID level 1
  2. RAID level 2
  3. RAID level 0
  4. RAID level 3
Answer

RAID level 1
NIELIT 2017 OCT Scientific Assistant A (CS)

Q. The addressing mode/s, which uses the PC instead of a general-purpose register is :

  1. Indexed with offset
  2. Relative
  3. Direct
  4. Both are Indexed with offset and direct
Answer

Relative
NIELIT 2021 Dec Scientist A

Q. Which of the following is/are not features of RISC processors?
i. Large number of addressing modes.
ii. Uniform instruction set.

  1. (i) Only
  2. (ii) Only
  3. Both (i) and (ii)
  4. None of the options
Answer

(i) Only
NIELIT 2017 DEC Scientist B

Q. Which of the following is false?

  1. Interrupts which are initiated by an instruction are software interrupts
  2. When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer
  3. A microprogram which is written as 0’s and 1’s is binary
  4. None of the options
Answer

None of the options
NIELIT 2017 DEC Scientist B

Q. What is virtual memory?

  1. An illusion of an extremely large memory, that is physically not present
  2. A type of memory used in nanocomputers
  3. A memory that is in direct touch with the CPU
  4. A memory that works on the principle of set associative mapping
Answer

An illusion of an extremely large memory, that is physically not present
NIELIT 2021 Dec Scientist B

Q. A stack-organized computer has which of the following instructions?

  1. zero-address
  2. one-address
  3. two-address
  4. three-address
Answer

zero-address
NIELIT 2017 DEC Scientist B

Q. Which open addressing technique is free from Clustering problems?

  1. Linear probing
  2. Quadratic probing
  3. Double hashing
  4. Rehashing
Answer

Double hashing
NIELIT 2022 April Scientist B

Q. Match List I with List II and select the correct answer using the codes given below the lists.

List IList II
A.0-address instructioni.T=TOP(T-1)
B.1-address instructionii.Y=Y+X
C.2-address instructioniii.Y=A-B
D.3-address instructioniv.ACC=ACC – X
  1. A-i, B-ii, C-iii, D-iv
  2. A-iii, B-ii, C-iv, D-i
  3. A-ii, B-iii, C-i, D-iv
  4. A-i, B-iv, C-ii, D-iii
Answer

A-i, B-iv, C-ii, D-iii
NIELIT 2017 OCT Scientific Assistant A (CS)

Q. In a 10-bit computer instruction format, the size of the address field is 3-bits. The computer uses the expanding OP code technique and has 4 two-address instructions and 16 one-address instructions. The number of zero address instructions it can support is

  1. 256
  2. 356
  3. 640
  4. 756
Answer

640
NIELIT 2017 OCT Scientific Assistant A (IT)

Q. Cache memory works on the principle of :

  1. Locality of data
  2. Locality of memory
  3. Locality of reference
  4. Locality of reference & memory
Answer

Locality of reference
NIELIT 2021 Dec Scientist B

Q. The atomic fetch-and-set x,y instruction unconditionally sets the memory location x to 1 and fetches the old value of x in y without allowing any intervening access to the memory location x. Consider the following implementation of P and V functions on a binary semaphore S.

void P (binary_semaphore *s) {
unsigned y;
unsigned *x = &(s->value);
do {
fetch-and-set x, y;
} while (y);
}
void V (binary_semaphore *s) {
S->value = 0;
}

Which one of the following is true?

  1. The implementation may not work if context switching is disabled in P.
  2. Instead of using fetch-and–set, a pair of normal load/store can be used.
  3. The implementation of V is wrong.
  4. The code does not implement a binary semaphore.
Answer

The implementation of V is wrong.
NIELIT 2022 April Scientist B

Q. Consider a hard disk with 16 recording surfaces (0-15) having 16384 cylinders (0-16383) and each cylinder contains 64 sectors (0-63). Data storage capacity in each sector is 512 bytes. Data are organized cylinder-wise and the addressing format is <cylinder number, surface number, sector number>. A file of size 42797 KB is stored in the disk and the starting disk location of the file is <1200,9,40>. What is the cylinder number of the last sector of the file, if it is stored in a contiguous manner?

  1. 1281
  2. 1282
  3. 1283
  4. 1284
Answer

1283
NIELIT 2022 April Scientist B

Q. External Interrupt may not arise because of

  1. illegal or erroneous use of an instruction.
  2. a timing device.
  3. external source.
  4. I/O devices.
Answer

illegal or erroneous use of an instruction.
NIELIT 2016 DEC Scientist B (CS)

Q. MIMD stands for

  1. Multiple Instruction Multiple Data
  2. Multiple Instruction Memory Data
  3. Memory Instruction Multiple data
  4. Multiple Information Memory data
Answer

Multiple Instruction Multiple Data
NIELIT 2016 DEC Scientist B (IT)

Q. In a microprocessor, WAIT states are used to

  1. make the processor wait during a DMA operation
  2. make the processor wait during a power interrupt processing
  3. make the processor wait during a power shutdown
  4. interface slow peripherals to the processor
Answer

interface slow peripherals to the processor
NIELIT 2016 MAR Scientist C

Q. Consider a software program that is artificially seeded with 100 faults. While testing this program, 159 faults are detected, out of which 75 faults are from those artificially seeded faults. Assuming that both real and seeded faults are of the same nature and have the same distribution, the estimated number of undetected real faults is _____________ .

  1. 28
  2. 175
  3. 56
  4. 84
Answer

28
NIELIT Scientist B 2020 November

Q. An instruction used to set the carry flag in a computer can be classified as

  1. data transfer
  2. process control
  3. logical
  4. program control
Answer

logical
NIELIT 2016 MAR Scientist C

Q. CPU consists of ________.

  1. ALU and Control Unit
  2. ALU, Control Unit, and Monitor
  3. ALU, Control Unit, and Hard disk
  4. ALU, Control Unit, and Register
Answer

ALU, Control Unit and Register
NIELIT 2016 DEC Scientist B (CS)

Q. How many address lines are needed to address each memory location in a 2048×4 memory chip?

  1. 10
  2. 11
  3. 8
  4. 12
Answer

11
NIELIT 2016 DEC Scientist B (IT)

Q. Microprocessors are used in which generation of computers?

  1. I-st Generation
  2. II-nd Generation
  3. III-rd Generation
  4. IV-th Generation
Answer

IV-th Generation
NIELIT 2017 DEC Scientific Assistant A

Q. Microprogramming is a technique for

  1. writing small programs effectively
  2. programming output/input routines
  3. programming the microprocessors
  4. programming the control steps of a computer
Answer

programming the control steps of a computer
NIELIT 2016 MAR Scientist C

Q. A RAM chip has 7 address lines, 8 data lines and 2 chips select lines. Then the number of memory locations is _________.

  1. 212
  2. 210
  3. 219
  4. 213
Answer

212
NIELIT 2017 DEC Scientist B

Q. Assembly language ____________.

  1. uses mnemonics or alphabetic codes in place of binary numbers used in machine language
  2. is the easiest language to write programs
  3. need not be translated into machine language
  4. is a high-level language.
Answer

uses mnemonics or alphabetic codes in place of binary numbers used in machine language
NIELIT 2021 Dec Scientist B

Q. In classful addressing, a large part of the available addresses are __________.

  1. Dispersed
  2. Blocked
  3. Wasted
  4. Reserved
Answer

Wasted
NIELIT Scientist B 2020 November

Q. Which open addressing technique is free from Clustering problems?

  1. Linear probing
  2. Quadratic probing
  3. Double hashing
  4. Rehashing
Answer

Double hashing
NIELIT Scientist B 2020 November

Q. A direct mapped cache is of size 32 KB and has a block size of 32 Bytes. CPU also generates 32-bit address. Number of bits needed for indexing the cache

  1. 14
  2. 15
  3. 10
  4. 17
Answer

10
NIELIT Scientist B 2020 November

Q. One disk queue with requests for I/O to blocks on cylinders. The Request is in the following manner:
98 183 37 122 14 124 65 67
Considering SSTF (shortest seek time first) scheduling, the total number of head movements is, if the disk head is initially at 53 is:

  1. 236
  2. 246
  3. 220
  4. 240
Answer

236
NIELIT Scientist B 2020 November

Q. Consider the following two statements
I. A Hash function, which is used for computing digital signatures, is an injective function
II. An encryption technique such as DES performs a permutation on the elements of its input alphabet

  1. Both are false
  2. I is true, II is false
  3. II is true, I is false
  4. Both are true
Answer

II is true, I is false
NIELIT 2021 Dec Scientist B

Q. Which of the following is true?

  1. Unless enabled, a CPU will not be able to process interrupts
  2. Loop instructions cannot be interrupted till they complete
  3. A processor need not check for interrupts before executing a new instruction
  4. Only level-triggered interrupts are possible on microprocessors
Answer

Unless enabled, a CPU will not be able to process interrupts
NIELIT 2021 Dec Scientist B

Q. Which memory is difficult to interface with the processor?

  1. Static memory
  2. Dynamic memory
  3. ROM
  4. None of the option
Answer

Dynamic memory
NIELIT 2017 July Scientist B (CS)

Q. For a memory system, the cycle time is

  1. Same as the access time.
  2. Longer than the access time.
  3. Shorter than the access time.
  4. Multiple access times.
Answer

Longer than the access time.
NIELIT 2017 July Scientist B (CS)

Q. If main memory access time is 400μs, TLB access time 50μs, considering TLB hit 90%, what wil be the overall access time?

  1. 800 μs
  2. 490 μs
  3. 485 μs
  4. 450 μs
Answer

800 μs
NIELIT Scientist B 2020 November

Q. Consider a control unit generating the control signals. These control signals are divided into five mutually exclusive groups as shown below:

GroupsG1G1G1G1G1
Control Signals3710122

How many bits are saved using the Vertical Micro-programmed instead of the Horizontal Micro-programmed control unit?

  1. 14
  2. 34
  3. 20
  4. None
Answer

34
NIELIT Scientist B 2020 November

Q. _______ possible labels are allowed in the first level of the generic domain.

  1. 10
  2. 12
  3. 16
  4. none of the options
Answer

none of the options
NIELIT Scientist B 2020 November

Q. Consider a Simple Checkpointing Protocol and the following set of operations in the log.
(start,T4);(write,T4,y,2,3);(start,T1);
(commit,T4);(write,T1,z,5,7);
(Checkpoint);
(start,T2);(write,T2,x,1,9);
(commit,T2);(start,T3);(write,T3,z,7,2);
if a crash happens now and the system tries to recover using both undo and redo operations, what are the contents of the undo list and the redo list?

  1. Undo : T3,T1: Redo T2
  2. Undo : T3,T1: Redo T2,T4
  3. Undo : none: Redo T2,T4,T3,T1
  4. Undo : T3,T1,T4: Redo T2
Answer

Undo : T3,T1: Redo T2
NIELIT Scientist B 2020 November

Q. A 5-stage pipelined CPU has the following sequence of stages:
• IF – instruction fetch from instruction memory
• RD – Instruction decode and register read
• EX – Execute: operation for data and address computation
• MA – Data memory access – for write access, the register read at state is used.
• WB – Register to write back

Consider the following sequence of instructions:
• I1 : L R0, loc1; R0 <= M[loc1]
• I2 : A R0, R0; R0 <= R0 + R0
• I3 : S R2, R0; R2 <= R2 – R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1?

  1. 8
  2. 10
  3. 12
  4. 15
Answer

10
NIELIT 2022 April Scientist B

Q. Consider a software project with the following information domain characteristics for the calculation of function point metric.
• Number of external inputs (I) = 30
• Number of external outputs (O) = 60
• Number of external inquiries (E) = 23
• Number of files (F) = 08
• Number of external interfaces (N) = 02$
It is given that the complexity weighting factors for I, O, E, F, and N are 4,5,4,10, and 7 respectively. It is also given that, out of fourteen value adjustment factors that influence the development effort, four factors are not applicable, each of the other four factors has value 3, and each of the remaining factors has value 4. The computed value of the function point metric is _________.

  1. 612.06
  2. 212.05
  3. 305.09
  4. 806.9
Answer

612.06
NIELIT 2022 April Scientist B

Q. If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4×6 array, where each chip is 8K×4 bits?

  1. 13
  2. 14
  3. 16
  4. 17
Answer

17
NIELIT 2017 July Scientist B (CS)

Q. The physical location of a record is determined by a mathematical formula that transforms a file key into a record location is:

  1. B-Tree File
  2. Hashed File
  3. Indexed File
  4. Sequential File
Answer

Hashed File
NIELIT Scientist B 2020 November

Q. A 26-bit address bus has a maximum accessible memory capacity of _____________.

  1. 64 MB
  2. 16 MB
  3. 1 GB
  4. 4 GB
Answer

64 MB
NIELIT Scientific Assistant A 2020 November

Q. Consider a software project with the following information domain characteristic for the calculation of function point metric.
Number of external inputs (I) = 30
Number of external output (O) = 60
Number of external inquiries (E) = 23
Number of files (F) = 08
Number of external interfaces (N) = 02
It is given that the complexity weighting factors for I, O, E, F, and N are 4,5,4,10 and 7, respectively. It is also given that, out of fourteen value adjustment factors that influence the development effort, four factors are not applicable, each of the other four factors has value 3, and each of the remaining factors has value 4. The computed value of the unction point metric is ___________ .

  1. 612.06
  2. 212.05
  3. 305.09
  4. 806.9
Answer

612.06
NIELIT Scientist B 2020 November

Q. Contiguous memory allocation having variable size partition suffers from:

  1. External Fragmentation
  2. Internal Fragmentation
  3. Both External and Internal Fragmentation
  4. None of the options
Answer

External Fragmentation
NIELIT Scientist B 2020 November

Q. Which of the following is not a form of main memory?

  1. Instruction cache
  2. Instruction register
  3. Instruction opcode
  4. Translation look-aside buffer
Answer

Instruction opcode
NIELIT 2017 OCT Scientific Assistant A (CS)

Q. Micro program is

  1. the name of the source program in microcomputers
  2. the set of instructions indicating the primitive operations in a system
  3. primitive form of macros used in assembly language programming
  4. program of very small size
Answer

the set of instructions indicating the primitive operations in a system
NIELIT 2016 MAR Scientist C

Q. _________ is a partitioning of a single physical server into multiple logical servers.

  1. Virtualization
  2. Private cloud
  3. Hybrid cloud
  4. Public cloud
Answer

Virtualization
NIELIT Scientist B 2020 November

Q. In _______ VMs do not simulate the underlying hardware.

  1. Para Virtualization
  2. Full Virtualization
  3. Hardware-Assisted Virtualization
  4. Network Virtualization
Answer

Para Virtualization
NIELIT Scientist B 2020 November

Q. An application loads 100 libraries at startup. Loading each library requires exactly one disk access. The seek time of the disk to a random location is given as 10ms. The rotational speed of the disk is 6000 rpm. If all 100 libraries are loaded from random locations on the disk, how long does it take to load all libraries? (The time to transfer data from the disk block once the head has been positioned at the start of the block may be neglected)

  1. 0.50 s
  2. 1.50 s
  3. 1.25 s
  4. 1.00 s
Answer

1.00 s
NIELIT 2022 April Scientist B

  1. II and V only
  2. I, III, and IV only
  3. I, II, and V only
  4. II, III, and V only
Answer

I,II and V only
NIELIT 2022 April Scientist B

Q. In a data flow diagram, the segment shown below is identified as having transaction flow characteristics, with p2 identified as the transaction center. A first-level architectural design of this segment will result in a set of process modules with an associated invocation sequence. The most appropriate architecture is

  1. p1 invokes p2, p2 invokes either p3, or p4, or p5
  2. p2 invokes p1 and then invokes p3, or p4, or p5
  3. A new module Tc is defined to control the transaction flow. This module Tc first invokes p1 and then invokes p2. p2 then invokes p3, or p4, or p5
  4. A new module Tc is defined to control the transaction flow. This module Tc invokes p2. p2 invokes p1, and then invokes p3, or p4 or p5
Answer

A new module Tc is defined to control the transaction flow. This module Tc first invokes p1 and then invokes p2. p2 then invokes p3, or p4, or p5
NIELIT 2022 April Scientist B

Q. Consider the virtual page reference string
1,2,3,2,4,1,3,2,4,1
On a demand-paged virtual memory system running on a computer system the main memory size of 3 page frames which are initially empty. Let LRU, FIFO, and OPTIMAL denote the number of page faults under the corresponding page replacement policy. Then

  1. OPTIMAL < LRU < FIFO
  2. OPTIMAL < FIFO < LRU
  3. OPTIMAL = LRU
  4. OPTIMAL = FIFO
Answer

OPTIMAL < FIFO < LRU
NIELIT 2022 April Scientist B

Q. Consider a machine with a 40 MHz processor that has run a benchmark program. The executed program consists of 100,000 instruction executions, with the following instructions mix and clock cycle count. What will be the effective CPI, MIPS rate, and execution time?

Instruction TypeInstruction CountCycles/Instructions
Integer arithmetic450001
Data Transfer320002
Floating point150002
Control transfer80002
  1. CPI : 3.55; MIPS : 30; Execution time : 1.87 ms
  2. CPI : 1.55; MIPS : 25.8; Execution time : 3.87 ms
  3. CPI : 5.60; MIPS : 45.8; Execution time : 2.87 ms
  4. CPI : 2.55; MIPS : 35.8; Execution time : 4.87 ms
Answer

CPI : 1.55; MIPS : 25.8; Execution time : 3.87 ms
NIELIT 2022 April Scientist B

  1. p= 50 and q=100
  2. p= 50 and q=400
  3. p= 100 and q=50
  4. p= 400 and q=50
Answer

p= 400 and q=50
NIELIT 2022 April Scientist B

Q. An operating system uses the Banker’s algorithm for deadlock avoidance when managing the allocation of three resource types X,Y and Z to three processes P0,P1 and P2. The table given below presents the current system state. Here, the Allocation matrix shows the current number of resources of each type allocated to each process and the Max matrix shows the maximum number of resources of each type required by each process during its execution.

AllocationAllocationAllocationMAXMAXMAX
XYZXYZ
P0001843
P1320620
P2211333

There are 3 units of type X, 2 units of type Y and 2 units of type Z still available. The system is currently in a safe state. Consider the following independent requests for additional resources in the current state:
REQ1 : P0 requests 0 units of X, 0 units of Y and 2 units of Z
REQ2 : P1 requests 2 units of X, 0 units of Y and 0 units of Z
Which one of the following is TRUE?

  1. Only REQ1 can be permitted.
  2. Only REQ2 can be permitted.
  3. Both REQ1 and REQ2 can be permitted.
  4. Neither REQ1 nor REQ2 can be permitted.
Answer

Only REQ1 can be permitted.
NIELIT 2022 April Scientist B

Q. Which of the following techniques deals with sorting the data stored in the computer’s memory?

  1. Distribution sort
  2. Internal sort
  3. External sort
  4. Radix sort
Answer

Internal sort
NIELIT Scientist B 2020 November

Q. Consider a non-pipelined machine with 6 stages; the lengths of each stage are 20ns, 10ns, 30ns, 25ns, 40ns and 15ns respectively. Suppose for implementing the pipelining the machine adds 5ns of overhead to each stage for clock skew and set up. What is the speed up factor of the pipelining system (ignoring any hazard impact)?

  1. 7
  2. 14
  3. 3.11
  4. 22
Answer

3.11
NIELIT 2017 DEC Scientist B

Q. A page fault occurs when:

  1. the Deadlock happens
  2. the Segmentation starts
  3. the page is found in the memory
  4. the page is not found in the memory
Answer

the page is not found in the memory
NIELIT 2021 Dec Scientist B

Q. Consider a memory system where a request comes for disk driver for cylinders 10,22,20,2,40,6 and 38 (head start at 20). The seek time is 6 ms per cylinder. The total seek time if the disk arm scheduling algorithm is FCFS :

  1. 850 ms
  2. 906 ms
  3. 400 ms
  4. 876 ms
Answer

876 ms
NIELIT 2021 Dec Scientist B

Q. Consider the following two-phase locking protocol. Suppose a transaction T accesses (for read or write operations), a certain set of objects {O1,……,Ok. This is done in the following manner:
• Step 1 : T acquires exclusive locks to O1,……,Ok in increasing order of their addresses.
• Step 2 : The required operations are performed.
• Step 3 : All locks are released
This protocol will

  1. guarantee serializability and deadlock-freedom
  2. guarantee neither serializability nor deadlock-freedom
  3. guarantee serializability but not deadlock-freedom
  4. guarantee deadlock-freedom but not serializability.
Answer

guarantee serializability and deadlock-freedom
NIELIT 2022 April Scientist B

Q. We have 10-stage pipeline, where the branch target conditions are resolved at stage 5. How many stalls are there for an incorrectly predicted branch?

  1. 5
  2. 6
  3. 7
  4. 4
Answer

4
NIELIT 2017 DEC Scientist B

Q. A microprogrammed control unit :

  1. is faster than a hardwired control unit
  2. allows easy implementation of new instructions
  3. is useful when small programs are to be run
  4. none of the options
Answer

allows easy implementation of new instructions
NIELIT 2021 Dec Scientist A

Q. Consider three processes, all arriving at time zero, with a total execution time of 10,20 and 30 units, respectively. Each process spends the first 20% of execution time doing I/O, the next 70% of time doing computation, and the last 10% of time doing I/O again. The operating system uses the shortest remaining compute time first scheduling algorithm and schedules a new process either when the running process gets blocked on I/O or when the running process finishes its compute burst. Assume that all I/O operations can be overlapped as much as possible. For what percentage of time does the CPU remain idle?

  1. 0%
  2. 10.6%
  3. 30.0%
  4. 89.4%
Answer

0%
NIELIT 2022 April Scientist B

Q. Which of the following is the advantage of using the JDBC connection pool?

  1. Slow performance
  2. Using more memory
  3. Using less memory
  4. Better performance
Answer

Better performance
NIELIT 2021 Dec Scientist B

Q. Comparing the time T1 taken for a single instruction on a pipelined CPU, with time T2 taken on a non-pipelined but identical CPU, we can say that _________ ?

  1. T1=T2
  2. T1>T2
  3. T1<T2
  4. T1 is T2 plus the time taken for one instruction fetch cycle
Answer

T1>T2
NIELIT 2017 July Scientist B (CS)

Q. Consider a memory system in which the size of the page is 8 KB. A CPU that generates the 32-bit virtual address. What will be the minimum size of the TLB (translation lookaside buffer) tag, if TLB has ta otal 256-page table and is 8-way set associative?

  1. 12 bit
  2. 13 bit
  3. 14 bit
  4. 15 bit
Answer

14 bit
NIELIT 2021 Dec Scientist B

Q. A non-pipeline system takes 50ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determinants the speedup ratio of the pipeline for 100 tasks. What is the maximum speedup that can be achieved?

  1. 4.90,5
  2. 4.76,5
  3. 3.90,5
  4. 4.30,5
Answer

4.76,5
NIELIT 2016 DEC Scientist B (CS)

Q. Which of the following is false?

  1. The smallest and fastest computer imitating a brain working is called a quantum computer.
  2. A computer with a speed of around 100 million instructions per second with the word length of around 64 bits is known as super computer.
  3. The term Exa-byte=1024 Tera Bytes.
  4. None of the options.
Answer

The term Exa-byte=1024 Tera Bytes.
NIELIT 2017 DEC Scientist B

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