Digital Logic Gate Questions

Here, we will see Digital Logic GATE Questions from previous years’ papers and the Digital Logic for GATE Exam syllabus.

1. Digital Logic in Gate CSE Exam

Digital Logic is a foundational topic in the GATE Computer Science Engineering (CSE) syllabus, testing candidates’ understanding of Boolean algebra, combinational/sequential circuits, and number systems. Questions often focus on designing and optimizing logic circuits, minimizing expressions using Karnaugh Maps (K-Maps), and solving problems related to computer arithmetic, such as fixed/floating-point representations.

2. Digital Logic Syllabus

The syllabus for Digital Logic in GATE CSE includes:

1. Boolean Algebra: Laws, simplification, logic gates, and canonical forms.
2. Combinational Circuits: Design of adders, subtractors, multiplexers, and parity generators.
3. Sequential Circuits: Latches, flip-flops, counters, and finite state machines.
4. Minimization Techniques: K-Maps, Quine-McCluskey method.
5. Number Systems: Binary, hexadecimal, signed/unsigned representations.
6. Computer Arithmetic: Fixed-point operations, IEEE 754 floating-point standards, overflow handling.

Digital Logic Gate Questions

Q. Odd parity of word can be conveniently tested by

1. OR gate
2. AND gate
3. NOR gate
4. XOR gate

Q. The excess 3 code is also called

1. cyclic redundancy code
2. weighted code
3. self complimenting code
4. algebraic code

Q. How many inputs are required in Full Adder Circuit?

1. 2
2. 3
3. More than two inputs
4. None of the above

Q. In Boolean algebra 1+1+1+1….800 times ones=___________ .

1. 1
2. 0
3. 11
4. 800

Q. If A⊕B=C, then which one of the following is true?

1. A⊕C=B
2. B⊕C=A
3. A⊕B⊕C=0
4. Both (A) and (B)

Q. The possible number of Boolean function of 3 variables X,Y and Z and such that f(X,Y,Z)=f(X’,Y’,Z’)

1. 8
2. 16
3. 64
4. 32

Q. The complement of the expression Y = ABC+ABC’+A’B’C+A’BC is

1. (A’+B’)(A+C’)
2. (A’+B)(A+C)
3. (A+B’)(A’+C)
4. (A+B’)(A+C’)

Q. The logic expression for the output of following circuit is:

1. A’C+B’C+CD
2. AC’+BC’+C’D
3. ABC+C’D’
4. A’B’+B’C’+C’D’

Q. The spectral efficiency of QPSK null to null having a width 4 Hz will be

1. 1/2
2. 1
3. 1/4
4. 4

Q. (A+C’)(B’+C’) simplifies to

1. AC’+B’
2. C(A’+B’)
3. BC’+A
4. AB’+C’

Q. ________ number of gates are required to implement the Boolean function (AB+C) with using only 2-input NOR gates.

1. 2
2. 3
3. 4
4. 5

Q. Which of the following Boolean algebra rules is correct ?

1. A.Ā = 1
2. A+AB = A+B
3. A(A+B) = B
4. A+ĀB = A+B

Q. Baud rate measures the number of ______ transmitted per second

1. Symbols
2. Bits
3. Byte
4. None of these

Q. (a+b)² corresponds to the language

1. {a+b,a+b}
2. {aa,ab,ba,bb}
3. {abab,baba}
4. {a+b,(a+b)²}

Q. If data stored in AC=5F h and DR=C2 h, what is value of AC after ACΛDR operation?

1. 9D
2. 42
3. DF
4. DE

Q. In the given truth table, f(x,y) represent the Boolean function.

1. x↔y
2. xΛy
3. xVy
4. x→y

Q. Which of the following logic expression is incorrect?

1. 1⊕0 = 1
2. 1⊕1⊕0 = 1
3. 1⊕1⊕1 = 1
4. 1⊕1 = 0

Q. If integer means to 2 bytes of storage then maximum value of a signed integer is :

1. 2¹⁶-1
2. 2¹⁵-1
3. 2¹⁶
4. 2¹⁵

Q. A sequence of statement of the form x=y op z is called a

1. Three address code
2. Syntax tree
3. Postfix notation
4. Operator

Q. The postfix equivalent of the infix expression (a+b)*(c*d-e)*f/g is :

1. ab+cd*e-fg*/*
2. ab+cd*e-fg/**
3. ab+cde*-fg/**
4. abcd+e*fg-/**

Q. In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the

1. clock input of all flip-flops
2. clock input of one flip-flop
3. J and K inputs of all flip-flops
4. J and K inputs of one flip flop

Q. How many Addition and Subtraction are required if you perform multiplication of 5 (Multiplicand) and -30 (Multiplier) using Booth Algorithm?

1. 2,1
2. 1,2
3. 1,1
4. 2,2

Q. ABC*+ is the postfix form of :

1. A*B+C
2. A*+BC
3. A+B*C
4. none of these

Q. What happens when a bit string is XORed with itself n times as shown below ?
[B⊕(B⊕(B⊕(B……….. n times]

1. Complements when n is even
2. Complements when n is odd
3. Divides by 2ⁿ always
4. Remains unchanged when n is even

Q. In which of the following adder circuits, the carry look ripple delay is eliminated?

1. Half adder
2. Full adder
3. Parallel adder
4. Carry-look ahead adder

Q. Equalization process includes:

1. maximum likelihood sequence estimation and equalization with filters
2. maximum likelihood sequence estimation
3. equalization with filters
4. constant impulse response

Q. Which of the following Boolean expressions is not logically equivalent to all of the rest?

1. ab+(cd)’+cd+bd’
2. a(b+c)+cd
3. ab+ac+(cd)’
4. bd’+c’d’+ab+cd

Q. The Circuit is equivalent to:

1. OR Gate
2. NOR Gate
3. AND Gate
4. EX-OR Gate

Q. How many RAM chips of size (256K×1bit) are required to build 1M Byte memory?

1. 8
2. 10
3. 24
4. 32

Q. Let f(A,B) = Ā+B, Simplified expression for function f(f(x+y,y),z) is

1. x’+z
2. xyz
3. xy’+z
4. None of the options

Q. To make the following circuit a tautology ‘?’ marked box should be

1. OR gate
2. AND gate
3. NAND gate
4. EX-OR gate

Q. In the following gate network which gate is redundant?

1. Gate no. 1
2. Gate no. 2
3. Gate no. 3
4. Gate no. 4

Q. The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent?

1. NOT
2. OR
3. AND
4. XOR

Q. Convert (503201)₆ into (?)₄

1. 12122231
2. 11000011
3. 21222301
4. 22323301

Q. The number of full and half-adders required to add 16-bit numbers is

1. 8 half-adders, 8 full-adders
2. 1 half-adders, 15 full-adders
3. 16 half-adders, 0 full-adders
4. 4 half-adders, 12 full-adders

Q. The bit rate of digital communication system is R kbit/s. The modulation used is 32-QAM. The minimum bandwidth required for ISI free transmission is

1. R/10 Hz
2. R/10 KHz
3. R/5 Hz
4. R/5 KHz

Q. If the value of Register A=9B h & Carry=1. What will be the value of Register A after executing the RORC instruction 1 time?

1. AB h
2. CD h
3. EF h
4. AC h

Q. Which one of the following is true?

1. NAND gate and AND gate both are universal gates
2. NOR gate and OR gate both are universal gates
3. NAND gate and OR gate both are universal gates
4. NAND gate and NOR gate both are universal gates

Q. Minimum _ full adders and _ half adders are required by the BCD adder to add two decimal digits.

1. 3,2
2. 9,4
3. 6,5
4. 5,2

Q. Encodes are made by three ______ gates.

1. AND
2. OR
3. NAND
4. XOR

Q. How many AND, OR and XOR gates are required for implementation of full adder?

1. 1,2,2
2. 2,2,1
3. 3,2,2
4. 3,0,1

Q. The two numbers represented in Signed 2’s complement form are A=11101101 and B=11100110. If B is subtracted from A, the value obtained in signed 2’s complement is

1. 111000101
2. 00000111
3. 11111000
4. 10000011

Q. If for the matrix A, A³=I, then A^-1=__________ .

1. A²
2. A³
3. A
4. None of these

Q. A RAM chip has a capacity of 1024 words of 8 bits each (1K×8). The number of 2×4 decoders with enable line needed to construct a 32K×8 RAM from 1K×8 RAM is

1. 4
2. 5
3. 6
4. 7

Q. A 4-bit ripple counter and a 4-bit synchronous counter are made using flip-flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

1. R=10ns, S=40ns
2. R=40ns, S=10ns
3. R=10ns, S=30ns
4. R=30ns, S=10ns

Q. When factorizing the Boolean equation Y=AB’+AB, the result will be :

1. AB’
2. AB
3. A
4. B

Q. If the input J is connected through K input of J-K, then flip-flop will behave as a

1. D type flip-flop
2. T type flip-flop
3. S-R flip-flop
4. Toggle switch

Q. To build a mod-19 counter the number of flip-flop required is

1. 3
2. 5
3. 7
4. 8

Q. A binary sequence b[n] is given as shown below
b[n] = {0,1,1,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0,0,0,1,1,0,1}
Consider the following statements regarding the above coded sequence :
i. It has a DC null in the PSD.
ii. It possesses error detecting capability.
iii. It possesses error correcting capability.
iv. It facilitates clock recovery at the receiver.
Which of the above statements are true?

1. i, iii and iv
2. i, ii and iv
3. i, ii and iii
4. ii, iii and iv

Q. Which of the following conditions must be met to avoid race around problem?

1. ∆t < tp < T
2. T > ∆t > tp
3. 2tp < ∆t < T
4. none of these

Q. The following circuit depicts the implementation of __________

1. XOR Gate
2. AND Gate
3. OR Gate
4. NAND Gate

Q. Which of the following is minimum error code?

1. Octal Code
2. Binary Code
3. Gray Code
4. Excess-3 Code

Q. How many flip-flop are needed to divide the input frequency by 64?

1. 4
2. 5
3. 6
4. 8

Q. Which will be the equation of simplification of the given K-map?

1. AB’+B’CD’+A’B’C’
2. AB’+A’B’D’+A’B’C’
3. B’D’+AB’+B’C’
4. B’D’+A’B’C’+AB’

Q. What will be the equation of the given K-map?

1. A’B’D’+C’D+AB’C’
2. B’CD’+AB’C’+A’C’
3. B’D’+C’D
4. C’D+B’CD’

Q. A demultiplexer is used to :

1. Route the data from single input to one of many outputs
2. Perform serial to parallel conversion
3. Both 1 and 2
4. Select data from several inputs and route it to single output

Q. The digital multiplexer is basically a combination logic circuit to perform the operation

1. AND-AND
2. OR-OR
3. AND-OR
4. OR-AND

Q. Which one of the following is the function of a multiplexer?

1. To decode information
2. To select 1 out of N input data sources and to transmit it to single channel
3. To transmit data on N lines
4. To perform serial to parallel conversion

Q. How many 2-input multiplexers are required to construct a 2¹⁰ input multiplexer?

1. 1023
2. 31
3. 10
4. 127

Q. In DPSK technique, the technique used to encode bits is:

1. AMI
2. Differential code
3. Unipolar RZ format
4. Manchester format

Q. The hexadecimal representation of 632₈ is

1. 19A
2. 198
3. 29A
4. 291

Q. What will be the Excess-3 code for 1001?

1. 1001
2. 1010
3. 1011
4. 1100

Q. The Decimal equivalent of the Hexadecimal number A09D₁₆ is

1. 31845
2. 41117
3. 41052
4. 32546

Q. What is 2’s complement of 101₃?

1. 010₃
2. 011₃
3. 121₃
4. 121₃

Q. Consider a combination of T and D flip-flops connected as shown below. The output of the D flipflop is connected to the input of the T flip-flop and the output of the flip-flop is connected to the input of the D flip-flop. Initially, both Q₀ and Q₁ are set to 1(before the 1^st clock cycle). The outputs _______

1. Q₀Q₁ after the 3^rd cycle are 11 and after the 4^th cycle are 00 respectively
2. Q₀Q₁ after the 3^rd cycle are 11 and after the 4^th cycle are 01 respectively
3. Q₀Q₁ after the 3^rd cycle are 00 and after the 4^th cycle are 11 respectively
4. Q₀Q₁ after the 3^rd cycle are 01 and after the 4^th cycle are 01 respectively

Q. Disadvantage of dynamic RAM over static RAM is

1. higher power consumption.
2. variable speed.
3. need to refresh the capacitor charge every once in two milliseconds.
4. higher bit density.

Q. The Decimal equivalent of the Hexadecimal number AC7B₁₆ is:

1. 32564
2. 44155
3. 50215
4. 43562

Q. A decimal number has 30 digits. Approximately, how many digits would the binary representation have?

1. 30
2. 60
3. 90
4. 120

Q. The result of the subtraction FD₁₆ – 88₁₆ is

1. 75₁₆
2. 65₁₆
3. 5E₁₆
4. 10₁₆

Q. The smallest integer that can be represented by an 8-bit number in 2’s complement form is :

1. -256
2. -128
3. -127
4. 0

Q. The number 25₆, in base 6 is equivalent to __________ in binary number system.

1. 11001
2. 10001
3. 11000
4. 10000

Q. In a binary data transmission DPSK is preferred to PSK because :

1. a coherent carrier is not required to be generated at the receiver
2. for a given energy per bit, the probability of error is less
3. the 1800 phase shifts of the carrier are unimportant
4. more protection is provided against impulse noise

Q. A decimal has 25 digits. The number of bits needed for its equivalent binary representation is approximately,

1. 50
2. 74
3. 40
4. 60

Q. The range of the numbers which can be stored in an eight bit register is

1. -128 to +127
2. -128 to +128
3. -999999 to +999999
4. none of these

Q. What will be the final output of D Flip-Flop, if the input string is 11010011?

1. 1
2. 0
3. Don’t Care
4. None of the above

Q. Given the function F=P’+QR, where F is a function in three Boolean variables P,Q and R and P’=!P, consider the following statements.
S₁ : F = ∑(4,5,6)
S₂ : F = ∑(0,1,2,3,7)
S₃ : F = ∏(4,5,6)
S₄ : F = ∏(0,1,2,3,7)
Which of the following is true?

1. (S₁)-False, (S₂)-True, (S₃)-True, (S₄)-False
2. (S₁)-True, (S₂)-False, (S₃)-False, (S₄)-True
3. (S₁)-False, (S₂)-False, (S₃)-True, (S₄)-True
4. (S₁)-True, (S₂)-True, (S₃)-False, (S₄)-False

Q. What will be the final output of D flip-Flop if the input string is 0010011100?

1. 1
2. 0
3. Don’t Care
4. None of the above

Q. The output of a sequential circuit depends on

1. present inputs only
2. past inputs only
3. both present and past inputs
4. present outputs only

Q. A sequential circuit outputs a ONE when an even number (>0) of one’s are input; otherwise the output is ZERO. The minimum number of states required is

1. 0
2. 1
3. 2
4. 3

Q. If a clock with time period ‘T’ is used with n stage shift register, then output of final stage will be delayed by

1. nT sec
2. (n-1)T sec
3. n/T sec
4. (2n-1)T sec

Q. Consider the set of strings on {0,1} in which, every substring of 3 symbols has at most two zeros. For example, 001110 and 011001 are in the language, but 100010 is not. All strings of length less than 3 are also in the language. A partially completed DFA that accepts this language is shown below.
The missing arcs in the DFA are

Q. A sequential circuit using D flip-flop and logic gates is shown in Figure, where X and Y are the inputs and Z is the output. The circuit is

1. S-R Flip-flop with inputs X=R and Y=S
2. S-R Flip-flop with inputs X=S and Y=R
3. J-K Flip-flop with inputs X=J and Y=K
4. J-K Flip-flop with inputs X=K and Y=J

Q. The number of columns in a state table for a sequential circuit with ‘m’ flip flops and ‘n’ input is

1. m+n
2. m+2n
3. 2m+n
4. 2m+2n

Q. Consider the following 2 bit counter using T flip-flops following 0-2-3-1-0 sequence. What should be the value of x?

1. Q₂
2. Q₁+Q₂
3. Q₁⊕Q₂
4. Q₁⊕Q₂‘

Q. Maximum number of bits required to represent any character from ASCII code set is:

1. 10
2. 8
3. 7
4. 3

Q. The size of the physical address space of a processor is 2^P bytes. The word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size of each cache block 2^M words. For a K-Way set associative cache memory, the length (in number of bits) of the tag fields is:

1. P-N-M-W+logK
2. P-N-M-W-log₂K
3. P-N+log₂K
4. P-N-log₂K

Q. For a bit-rate of 8 kbps, the best possible values of the transmitted frequencies in a coherent binary FSK system are :

1. 16 kHz and 20 kHz
2. 20 kHz and 32 kHz
3. 20 kHz and 40 kHz
4. 32 kHz and 40 kHz

Q. The complement of the expression Y = ABC+ABC’+A’B’C+A’BC is

1. (A’+B’)(A+C’)
2. (A’+B)(A+C)
3. (A+B’)(A’+C)
4. (A+B’)(A+C’)

Q. One-megabyte memory storage in form of bytes is equal to __________ .

1. 1024 bytes
2. 1024² bytes
3. 1024³ bytes
4. 1024⁴ bytes

Q. Considering binary relationships, possible cardinality ratios are:

1. one:one
2. 1:N
3. M:N
4. All the options

Q. Flat top sampling of low pass signals _________

1. gives rise to aperture effect
2. implies oversampling
3. lead to aliasing
4. introducing delay distortion

Q. A bandlimited signal is sampled at the Nyquist rate. The signal can be recovered by passing the samples through :

1. an RC filter
2. an envelope detector
3. a PLL
4. an ideal low-pass filter with the appropriate bandwidth

Q. In context of analog & digital communication, as the length of a long-wire antenna is increased, ______________ .

1. the number of lobes also increase
2. the number of lobes decrease
3. efficiency increase
4. the number of nodes decreases

Q. A special PCM system uses 32 channels of data, one whose purpose is an identification (ID) and synchronization. The sampling rate is 4 kHz. The word length is 5 bits. Find the serial data rate.

1. 1280 kHz
2. 160 kHz
3. 320 kHz
4. 640 kHz

Q. The Circuit is equivalent to

1. EX-OR Gate
2. NAND Gate
3. OR Gate
4. AND Gate

Q. What is the basis of KVL?

1. Conservation of charge
2. Conservation of energy
3. Conservation of power
4. All of the options

Q. In which modulation discrete values of carrier frequencies is used to transmit binary data?

1. Phase Shift Keying
2. Amplitude Shift Keying
3. Frequency Shift Keying
4. Disk Shift Keying

Q. If x,y,z are Boolean variable then (x+y’)(x•y’+x•z)(x’•z’+y’) is equal to

1. x•y’
2. x•y’+z
3. x•z’
4. none of the options

Q. Which flip-flop is used to make all types of shift registers?

1. JK flip-flop
2. D flip-flop
3. T flip-flop
4. All the options