COA Gate Questions

Here, We will see (Computer Organization and Architecture) COA GATE Questions from previous year’s papers and the syllabus of Computer Organization and Architecture for GATE Exam.

1. Computer Organization and Architecture in Gate CSE Exam

Computer Organization and Architecture (COA) is a critical subject in the GATE Computer Science and Information Technology (CS/IT) exam, testing candidates’ understanding of hardware functionality, system design, and operational efficiency. This subject bridges theoretical concepts with real-world applications, making it essential for both academic and industry roles.

2. Computer Organization and Architecture Syllabus

The syllabus for Computer Organization and Architecture in GATE CSE includes:

1. Machine Instructions & Addressing Modes: Basics of instruction sets, operand addressing, and register structures.
2. ALU, Data Path, & Control Unit: Design of arithmetic logic units and control mechanisms.
3. Instruction Pipelining: Stages of pipelining, hazards (structural, data, control), and optimization techniques.
4. Memory Hierarchy: Cache memory (associativity, hit/miss ratios), main memory, secondary storage, and virtual memory.
5. I/O Interfaces: Interrupts, DMA modes, and I/O processor communication.

(Computer Organization and Architecture) COA Gate Questions

1. Consider the following program segment. Here R₁, R_2, and R₃ are the general-purpose registers.

Assume that the content of memory location 3000 is 10 and the content of the register R₃ is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word-addressable. The number of memory references for accessing the data in executing the program completely is:

1. 10
2. 11
3. 20
4. 21

2. Consider the following program segment. Here R₁, R_2, and R₃ are the general-purpose registers.

Assume that the content of memory location 3000 is 10 and the content of the register R₃ is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word-addressable. After the execution of this program, the content of memory location 2010 is:

1. 100
2. 101
3. 102
4. 110

3. Consider the following program segment. Here R₁, R_2, and R₃ are the general-purpose registers.

Assume that the content of memory location 3000 is 10 and the content of the register R₃ is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is byte-addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction ‘INC R3’, what return address will be pushed onto the stack?

1. 1005
2. 1020
3. 1024
4. 1040

4. Which of the following is/are true of the autoincrement addressing mode?
(i) It is useful in creating self-relocating code
(ii) If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
(iii) The amount of increment depends on the size of the data item accessed

1. (i) only
2. (ii) only
3. (iii) only
4. (ii) and (iii) only

5. Consider a hypothetical processor with an instruction of type LW R₁, 20(R₂), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R₁. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R₂. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

1. Immediate addressing
2. Register addressing
3. Register indirect scaled addressing
4. Base indexed addressing

6. Consider two processors P₁ and P₂ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P₂ takes 25% less time but incurs 20% more CPI (Clock cycles per instructions) as compared to the program running on P₁. If the clock frequency of P₁ is 1GHz, then the clock frequency of P₂ (in GHz) is __.

1. 1.25
2. 0.75
3. 1.6
4. 0.98

7. A machine has a 32-bit architecture with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is __.

1. 0.73
2. 0.98
3. 1.63
4. 1.58

8. Consider a new instruction named branch-on-bitset (mnemonic bbs). The instruction ‘bbs reg, pos, label’ jump to label’ if a bit in position pos of register operand reg is one. A register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented.
temp ← reg & mask
Branch to label if temp is non-zero.
The variable temp is a temporary register. For correct emulation, the variable mask must be generated by

1. mask ← 0 × 1 << pos
2. mask ← 0 × ffffffff >> pos
3. mask ← pos
4. mask ← 0 × f

9. Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)₁₆ and it grows upward. The stack pointer (SP) points to the top element of CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:
1. Store the current value of PC in the stack
2. Store the value of PSW register in the stack
3. Load the starting address of the subroutine in PC
The content of PC just before the fetch of a CALL instruction is (5FA0)₁₆. After execution of the CALL instruction, the value of the stack pointer is

1. (016A)₁₆
2. (016C)₁₆
3. (0170)₁₆
4. (0172)₁₆

10. A processor has 40 distinct instructions and 24 general-purpose registers. A 32-bit instruction word has an opcode, two register operands, and an immediate operand. The number of bits available for the immediate operand field is __.

1. 8
2. 16
3. 24
4. 32

11. Suppose the functions F and G can be computed in 5 and 3 nanoseconds by functional units U_F and U_G, respectively. Given two instances of U_F and two instances of U_G, it is required to implement the computation F (G(X_i)) for 1 ≤ i ≤ 10. Ignoring all other delays, the minimum time required to complete this computation is _ nanoseconds.

1. 28
2. 16
3. 25
4. 36

12. Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _.

1. 350
2. 465
3. 500
4. 535

13. Consider the C struct defined below:

struct data {
  int marks[100];
  char grade;
  int cnumber;
};
struct data student;

The base address of student is available in register R1. The field student.grade can be accessed efficiently using

1. Post-increment addressing mode, (R1)+
2. Pre-decrement addressing mode, − (R1)
3. Register direct addressing mode, R1
4. Index addressing mode, X(R1), where X is an offset represented in 2’s complement 16-bit representation.

14. Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode Offset specified in bytes to the target location of the branch instruction. Further, the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence.

If the target of the branch instruction is i, then the decimal value of the Offset is ______ .

1. 16
2. -16
3. -8
4. 8

15. A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R + 1F). Type-4 category consists of Ninstructions, each with a floating point register operand (1F). The maximum value of N is __.

1. 8
2. 16
3. 4
4. 32

16. Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is _.

1. 1
2. 2
3. 3
4. 4

17. Consider the following processors (ns stands for nano-seconds). Assume that the pipeline registers have zero latency.
P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
Which processor has the highest peak clock frequency?

1. P1
2. P2
3. P3
4. P4

18. An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register to write back (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions that execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is _.

1. 0.76
2. 0.52
3. 3.48
4. 1.54

19. Consider an instruction pipeline with four stages (S₁, S₂, S₃ and S₄) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.
What is the approximate speed up of the pipeline in a steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

1. 4.0
2. 2.5
3. 1.1
4. 3.0

20. Register renaming is done in pipelined processors

1. as an alternative to register allocation at compile time
2. for efficient access to function parameters and local variables
3. to handle certain kinds of hazards
4. as part of address translation

21. Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI), and Write Operand (WO). The stage delays for FI, DI, FO, EI, and WO are 5 ns, 7 ns, 10 ns, 8 ns, and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I₁, I₂, I₃, ….., I₁₂ is executed in this pipelined processor. Instruction I₄ is the only branch instruction and its branch target is I₉. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

1. 132
2. 165
3. 176
4. 328

22. Delayed branching can help in the handling of control hazards. For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false

1. The instruction following the conditional branch instruction in memory is executed
2. The first instruction in the fall-through path is executed
3. The first instruction in the taken path is executed
4. The branch takes longer to execute than any other instruction

23. Delayed branching can help in the handling of control hazards. The following code is to run on a pipelined processor with one branch delay slot:
I₁ : ADD R₂ ← R₇ + R₈
I₂ : SUB R₄ ← R₅ – R₆
I₃ : ADD R₁ ← R₂ + R₃
I₄ : STORE Memory [R₄] R₁
BRANCH to Label if R₁ = 0
Which of the instructions I₁, I₂, I₃ or I₄ can legitimately occupy the delay slot without any other program modification?

1. I₁
2. I₂
3. I₃
4. I₄

24. A 5-stage pipelined CPU has the following sequence of stages:
IF – Instruction fetch from instruction memory
RD – Instruction decode and register read
EX – Execute: ALU operation for data and address computation
MA – Data memory access – for write access, the register read at RD state is used
WB – Register to write back
Consider the following sequence of instructions.
I₁ : L R₀, loc₁; R₀ <= M[loc₁]
I₂ : A R₀, R₀; R₀ <= R₀ + R₀
I₃ : S R₂, R₀; R₂ <= R₂ – R₀
Let each stage take one clock cycle. What is the number of clock cycles taken to complete the above sequence of instructions from the fetch of I₁?

1. 8
2. 10
3. 12
4. 15

25. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed-up achieved in this pipelined processor is __.

1. 2.6
2. 3.0
3. 3.2
4. 4.8

26. Consider the sequence of machine instructions given below:
MUL R₅, R₀, R₁
DIV R₆, R₂, R₃
ADD R₇, R₅, R₆
SUB R₈, R₇, R₄
In the above sequence, R0 to R8 are general-purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB). The IF, OF, and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction, and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is _.

1. 9
2. 12
3. 13
4. 18

27. Consider the following reservation table for a pipeline having the stages S₁, S_2, and S₃.

The minimum average latency (MAL) is __

1. 1
2. 2
3. 3
4. 5

28. Consider the following code sequence having five instructions l₁ to l₅. Each of these instructions has the following format.
OP Ri, Rj, Rk
Where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.
I₁: ADD R₁, R₂, R₃
I₂: MUL R₇, R₁, R₃
I₃: SUB R₄, R₁, R₅
I₄: ADD R₃, R₂, R₄
I₅: MUL R₇, R₈, R₉
Consider the following three statements.
S₁: There is an anti-dependence instruction between instructions I₂ and I₅
S₂: There is an anti-dependence between Instructions I₂
S₃: Within an instruction pipeline an anti-dependence always creates one or more stalls
Which one of the above statements is/are correct?

1. Only S₁ is true
2. Only S₂ is true
3. Only S₁ and S₃ are true
4. Only S₂ are true

29. The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays of 600 and 350 picoseconds. The throughput increase of the pipeline is _ percent.

1. 15.0 : 16.0
2. 22.5 : 23.5
3. 33.0 : 34.0
4. 38.3 : 39:3

30. Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies τ₁,τ₂ and τ₃ such that τ₁ = 3τ₂/4 = 2τ₃. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ________ GHz, ignoring delays in the pipeline registers.

1. 1
2. 4
3. 11
4. 6

31. Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode(ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implement action of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:
(i) A navie pipeline implementation (NP) with 5 stages and
(ii) An efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is __________ .

1. 1.51
2. 1.96
3. 0.64
4. 2.65

32. The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO), and Write back (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instructions is __.

1. 116
2. 172
3. 219
4. 200

33. A device with a data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 msec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode?

1. 15
2. 25
3. 35
4. 45

34. A computer handles several interrupt sources of which the following are relevant for this question.
i. Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high)
ii. Interrupt from Mouse (raises interrupt if the mouse is moved or a button is pressed)
iii. Interrupt from Keyboard (raises interrupt when a key is pressed or released)
iv. Interrupt from Hard Disk (raises interrupt when a disk read is completed)
Which one of these will be handled at the HIGHEST priority?

1. Interrupt from Hard Disk
2. Interrupt from Mouse
3. Interrupt from Keyboard
4. Interrupt from CPU temperature sensor

35. Consider the following program segment for a hypothetical CPU having three user registers R₁, R₂ and R₃. Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

1. 1007
2. 1020
3. 1024
4. 1028

36. Consider the following program segment for a hypothetical CPU having three user registers R₁, R₂ and R₃. Let the clock cycles required for various operations be as follows:
Register to/from memory transfer: 3 clock cycles
ADD with both operands in register: 1 clock cycle
Instruction fetch and decode: 2 clock cycles per word
The total number of clock cycles required to execute the program is

1. 29
2. 24
3. 23
4. 20

37. A CPU generally handles an interrupt by executing an interrupt service routine

1. As soon as an interrupt is raised.
2. By checking the interrupt register at the end of fetch cycle.
3. By checking the interrupt register after finishing the execution of the current instruction.
4. By checking the interrupt register at fixed time intervals.

38. A hard disk with a transfer rate of 10 Mbytes/second is constantly transferring data to memory using DMA. The processor runs at 6000 MHz and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes, what is the percentage of processor time consumed for the transfer operation?

1. 5.0%
2. 1.0%
3. 0.5%
4. 0.1%

39. On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register.
Initialize the count to 500
LOOP: Load a byte from the device
Store in memory at the address given by the address register.
Increment the address register
Decrement the count
If count! = 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.
The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller-based design is used in place of the interrupt-driven program-based input-output?

1. 3.4
2. 4.4
3. 5.1
4. 6.7

40. Which of the following statements about synchronous and asynchronous I/O is NOT true?

1. An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O
2. In both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is invoked after completion of the I/O
3. A process making a synchronous I/O call waits until the I/O is complete, but a process making an asynchronous I/O call does not wait for the completion of the I/O
4. In the case of synchronous I/O, the process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O

41. A main memory unit with a capacity of 4 megabytes is built using 1M × 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is

1. 100 nanoseconds
2. 100 * 2¹⁰ nanoseconds
3. 100 * 2²⁰ nanoseconds
4. 3200 * 2²⁰ nanoseconds

42. A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _ bits.

1. 25
2. 17
3. 31
4. 9

43. The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from the disk to the main memory. The memory is byte-addressable. The minimum number of times the DMA controller needs to get control of the system bus from the processor to transfer the file from the disk to main memory is ______ .

1. 256
2. 278
3. 374
4. 456

44. The following are some events that occur after a device controller issues an interrupt while process L is under execution.
(P) The processor pushes the process status of L onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of L from the control stack.
(T) The processor loads the new PC value based on the interrupt.
Which one of the following is the correct order in which the events above occur?

1. QPTRS
2. PTRSQ
3. TRPQS
4. QTPRS

45. A 32-bit wide main memory unit with a capacity of 1 GB is built using 256 M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2¹⁴. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read-write operations in the main memory unit is __.

1. 12 to 13
2. 33 to 34
3. 45 to 46
4. 59 to 60

46. Consider the following data path of a CPU.
The ALU, the bus, and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation—the first one for loading addresses in the MAR and the next one for loading data from the memory bus into the MDR. The instruction ‘add R₀, R₁’ has the register transfer interpretation R₀ ← R₀ + R₁. The minimum number of clock cycles needed for the execution cycle of this instruction is

1. 2
2. 3
3. 4
4. 5

47. Consider the following data path of a CPU.
The ALU, the bus, and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation—the first one for loading addresses in the MAR and the next one for loading data from the memory bus into the MDR. The instruction ‘call Rn, sub’ is a two-word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is
Rn ← PC + 1;
PC ← M[PC]
The minimum number of CPU clock cycles, needed during the execution cycle of this instruction is

1. 2
2. 3
3. 4
4. 5

48. Consider the following floating point format. Mantissa is a pure fraction in sign-magnitude form. The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0 ′s are padded in while shifting a field. The normalized representation of the above number (0.239 × 2¹³) is:

1. 0A 20
2. 11 34
3. 49 D0
4. 4A E8

49. In the IEEE floating point representation the hexadecimal value 0x00000000 corresponds to

1. The normalized value 2^-127
2. The normalized value 2^-126
3. The normalized value + 0
4. The special value + 0

50. P is a 16-bit signed integer. The 2’s complement representation of P is (F87B)₁₆. The 2’s complement representation of 8*P is

1. (C3D8)₁₆
2. (187B)₁₆
3. (F878)₁₆
4. (987B)₁₆

51. The decimal value 0.5 in IEEE single precision floating point representation has

1. fraction bits of 000 … 000 and exponent value of 0
2. fraction bits of 000…000 and exponent value of –1
3. fraction bits of 100…000 and exponent value of 0
4. no exact representation

52. The smallest integer that can be represented by an 8-bit number in 2’s complement form is

1. –256
2. –128
3. –127
4. 0

53. Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s complement is

1. 1100 0100
2. 1001 1100
3. 1010 0101
4. 1101 0101

54. The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields, a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y), there are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

1. 10, 3, 1024
2. 8, 5, 256
3. 5, 8, 2048
4. 10, 3, 512

55. Consider the following sequence of micro-operations.
MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR
Which one of the following is a possible operation performed by this sequence?

1. Instruction fetch
2. Operand fetch
3. Conditional branch
4. Initiation of interrupted service

56. For computers based on three-address instruction formats, each address field can be used to specify which of the following:
(S₁) A memory operand
(S₂) A processor register
(S₃) An implied accumulator register

1. Either S₁ or S₂
2. Either S₂ or S₃
3. Only S₂ and S₃
4. All of S₁, S₂ and S₃

57. Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign-magnitude representation. They x – y is __ .

1. 0
2. 1
3. 2
4. 3

58. The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part. Let i = n − f. The range of decimal values for X in this representation is

1. 2^{− f} to 2ⁱ
2. 2^{− f} to (2ⁱ − 2^{− f})
3. 0 to 2ⁱ
4. 0 to (2ⁱ − 2^{− f})

59. Consider the C code fragment given below.

typedef struct node {
  int data;
  node * next;
}
node;
void join(node * m, node * n) {
  node * p = n;
  while (p −> next != NULL) {
    p = p −> next;
  }
  p −> next = m;
}

Assuming that m and n point to valid NULLterminated linked lists, invocation of the join will

1. append list m to the end of list n for all inputs.
2. either cause a null pointer dereference or append list m to the end of list n.
3. cause a null pointer dereference for all inputs.
4. append list n to the end of list m for all inputs.

60. The representation of the value of a 16-bit unsigned integer X in hexadecimal number system is BCA9. The representation of the value of X in octal number system is

1. 571244
2. 736251
3. 571247
4. 136251

61. Consider the following processor design characteristics.
I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit
Which of the characteristics above are used in the design of a RISC processor?

1. I and II only
2. II and III only
3. I and III only
4. I, II and III

62. Consider the unsigned 8-bit fixed point binary number representation below:
b₇ b₆ b₅ b₄ b₃ ⋅ b₂ b₁ b₀
where the position of the binary point is between b₃ and b₂. Assume b₇ is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:
(i) 31.500
(ii) 0.875
(iii) 12.100
(iv) 3.001
Which one of the following statements is true?

1. None of (i), (ii), (iii), (iv) can be exactly represented
2. Only (ii) cannot be exactly represented
3. Only (iii) and (iv) cannot be exactly represented
4. Only (i) and (ii) cannot be exactly represented